1. Technical Field
The embodiments described herein relate to a semiconductor memory apparatus, and, more particularly, to a semiconductor memory apparatus capable of controlling a rank and a bank block.
2. Related Art
In general, in a semiconductor memory apparatus, a rank represents a unit memory chip controlled by one chip select signal and having an individual function. A single rank or a plurality of ranks can be employed according to the structure of the semiconductor memory apparatus. In order to activate the rank, a chip select signal ‘CS’ or a chip enable signal ‘CE’ can be used. Accordingly, each rank is attached to a printed circuit board (PCB) in the form of a unit memory chip having a plurality of semiconductor memory cells and is connected to a panel through a plurality of connectors. Thus, all memory cells belonging to the same rank share buses for chip select signals, commands, and address signals. Accordingly, when an MRS command is transferred through an address bus, DRAM apparatus provided in the same rank are set to the same operation mode.
Meanwhile, in a semiconductor memory apparatus driving a plurality of ranks by using a plurality of chip select signals, respectively, it is difficult to drive the plural ranks as multiple ranks or a single rank by using one chip select signal.